Journal of Engineering Sciences

EFFICIENT ADD-SUB DESIGN USING REVERSIBLE LOGIC GATES

M.SUNEETHA, K.BALA , SITS, PUNE

Page No :1-5

DOI:10.15433.JES.2019.Vol 3 Issue 2.43P.1

PROJECT ON 14 TRANSISTOR FULL ADDER CIRCUIT USING 4 TRANSISTOR XOR GATE AND TRANSMISSION GATE

P.SUNIL KUMAR , RLBR.PRASAD RAI, K.BALA CHANDRAN , CITS, JAIPUR

Page No :6-11

DOI:10.15433.JES.2019.Vol 3 Issue 2.43P.2

The WCN Basics and Control Methodologies for Networked Control Systems

M.SUNDARRAJAN1,DR.SIDDAPPA NAIDU2 , 1Sathayabama Univesity, Chennai,2Veltech University, Chennai

Page No :12-19

DOI:10.15433.JES.2019.V3I2.43P.3

An Energy-Efficient Duty-Cycled Wake-Up Radio Protocol For Avoiding Eavesdrop in Wireless Sensor Networks

M.SUNDARRAJAN1,DR.SIDDAPPA NAIDU2 , 1Sathayabama Univesity, Chennai,2Veltech University, Chennai

Page No :20-29

DOI:10.15433.JES.2019.V3I2.43P.4